Index: debian/control =================================================================== RCS file: /repository/DTN2/debian/control,v retrieving revision 1.2 retrieving revision 1.3 diff -u -r1.2 -r1.3 --- debian/control 21 Mar 2006 18:55:16 -0000 1.2 +++ debian/control 7 Jun 2006 21:59:53 -0000 1.3 @@ -2,7 +2,7 @@ Section: net Priority: optional Maintainer: Michael Demmer [demmer@cs.berkeley.edu] -Build-Depends: make, gcc, g++, debhelper (>= 4), tcl8.4-dev, libdb4.3-dev +Build-Depends: make, gcc, g++, debhelper (>= 4), tcl8.3-dev | tcl8.4-dev, libdb4.3-dev | libdb4.4-dev Package: dtn Architecture: any Index: oasys/Rules.make.in =================================================================== RCS file: /repository/oasys/Rules.make.in,v retrieving revision 1.23 diff -u -r1.23 Rules.make.in --- oasys/Rules.make.in 12 May 2006 18:07:56 -0000 1.23 +++ oasys/Rules.make.in 10 Aug 2006 12:59:23 -0000 @@ -3,7 +3,7 @@ # # -# Targets are "native" and "arm" +# Targets are "native", "arm" and "mips" # TARGET = @TARGET@ Index: debug/arith-mips.h =================================================================== RCS file: debug/arith-mips.h diff -N debug/arith-mips.h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ debug/arith-mips.h 7 Jun 2006 21:54:38 -0000 1.1 @@ -0,0 +1,6 @@ +#ifdef __mips__ +#define IEEE_MC68k +#define Arith_Kind_ASL 2 +#define Double_Align +#endif + Index: debug/arith-mipsel-linux.h =================================================================== RCS file: debug/arith-mipsel-linux.h diff -N debug/arith-mipsel-linux.h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ debug/arith-mipsel-linux.h 7 Jun 2006 21:54:38 -0000 1.1 @@ -0,0 +1,5 @@ +#ifdef __mips__ +#define IEEE_MC68k +#define Arith_Kind_ASL 2 +#define Double_Align +#endif Index: oasys/debug/StackTrace.cc =================================================================== RCS file: /repository/oasys/debug/StackTrace.cc,v retrieving revision 1.3 retrieving revision 1.8 diff -u -r1.3 -r1.8 --- oasys/debug/StackTrace.cc 15 Dec 2005 04:18:16 -0000 1.3 +++ oasys/debug/StackTrace.cc 14 Jun 2006 23:37:07 -0000 1.8 @@ -57,7 +57,8 @@ print_trace(stack + 2, count - 2); // skip this fn } else { char buf[1024]; - strncpy(buf, "NO STACK TRACE AVAILABLE ON THIS ARCHITECTURE\n", sizeof(buf)); + strncpy(buf, "NO STACK TRACE AVAILABLE ON THIS ARCHITECTURE\n", + sizeof(buf)); write(2, buf, strlen(buf)); } } @@ -98,16 +99,28 @@ #elif defined(__POWERPC__) || defined(PPC) #include "StackTrace-ppc.cc" -#else -#include +#elif HAVE_EXECINFO_H -// Generic stack trace function uses the glibc builtin +// Stack trace function using the glibc builtin +#include size_t StackTrace::get_trace(void* stack[], size_t size, u_int sighandler_frame) { + (void)sighandler_frame; return backtrace(stack, size); } +#else + +// Last resort -- just an no-op +size_t +StackTrace::get_trace(void* stack[], size_t size, u_int sighandler_frame) +{ + (void)sighandler_frame; + memset(stack, 0, size); + return 0; +} + #endif } // namespace oasys Index: oasys/thread/Atomic.h =================================================================== RCS file: /repository/oasys/thread/Atomic.h,v retrieving revision 1.12 retrieving revision 1.15 diff -u -r1.12 -r1.15 --- oasys/thread/Atomic.h 1 Feb 2006 19:05:40 -0000 1.12 +++ oasys/thread/Atomic.h 19 Jul 2006 00:05:30 -0000 1.15 #include "Atomic-x86.h" #elif defined(__POWERPC__) || defined(PPC) #include "Atomic-ppc.h" #elif defined(__arm__) #include "Atomic-arm.h" +#elif defined(__mips__) +#include "Atomic-mips.h" #elif defined(__win32__) #include "Atomic-win32.h" #else Index: thread/Atomic-mips.h =================================================================== RCS file: thread/Atomic-mips.h diff -N thread/Atomic-mips.h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ thread/Atomic-mips.h 7 Jun 2006 21:54:39 -0000 1.1 +#ifndef _OASYS_ATOMIC_MIPS_H_ +#define _OASYS_ATOMIC_MIPS_H_ + +namespace oasys { + +/** + * The definition of atomic_t for x86 is just a wrapper around the + * value, since we have enough synchronization support in the + * architecture. + */ +struct atomic_t { + atomic_t(u_int32_t v = 0) : value(v) {} + + volatile u_int32_t value; +}; + +/** + * Atomic addition function. + * + * @param i integer value to add + * @param v pointer to current value + * + */ +static inline u_int32_t +atomic_add_ret(volatile atomic_t *v, u_int32_t i) +{ + u_int32_t ret; + u_int32_t temp; + + __asm__ __volatile__( + " .set mips3 \n" + "1: ll %1, %2 # atomic_add_return \n" + " addu %0, %1, %3 \n" + " sc %0, %2 \n" + " beqzl %0, 1b \n" + " addu %0, %1, %3 \n" + " sync \n" + " .set mips0 \n" + : "=&r" (ret), "=&r" (temp), "=m" (v->value) + : "Ir" (i), "m" (v->value) + : "memory"); + + return ret; +} + +/** + * Atomic subtraction function. + * + * @param i integer value to subtract + * @param v pointer to current value + */ +static inline u_int32_t +atomic_sub_ret(volatile atomic_t * v, u_int32_t i) +{ + u_int32_t ret; + u_int32_t temp; + + __asm__ __volatile__( + " .set mips3 \n" + "1: ll %1, %2 # atomic_sub_return \n" + " subu %0, %1, %3 \n" + " sc %0, %2 \n" + " beqzl %0, 1b \n" + " subu %0, %1, %3 \n" + " sync \n" + " .set mips0 \n" + : "=&r" (ret), "=&r" (temp), "=m" (v->value) + : "Ir" (i), "m" (v->value) + : "memory"); + + return ret; +} + + +/// @{ +/// Wrapper variants around the basic add/sub functions above + +static inline void +atomic_add(volatile atomic_t* v, u_int32_t i) +{ + atomic_add_ret(v, i); +} + +static inline void +atomic_sub(volatile atomic_t* v, u_int32_t i) +{ + atomic_sub_ret(v, i); +} + +static inline void +atomic_incr(volatile atomic_t* v) +{ + atomic_add(v, 1); +} + +static inline void +atomic_decr(volatile atomic_t* v) +{ + atomic_sub(v, 1); +} + +static inline u_int32_t +atomic_incr_ret(volatile atomic_t* v) +{ + return atomic_add_ret(v, 1); +} + +static inline u_int32_t +atomic_decr_ret(volatile atomic_t* v) +{ + return atomic_sub_ret(v, 1); +} + +static inline bool +atomic_decr_test(volatile atomic_t* v) +{ + return (atomic_sub_ret(v, 1) == 0); +} + + + +/** + * Atomic compare and set. Stores the new value iff the current value + * is the expected old value. + * + * @param v pointer to current value + * @param o old value to compare against + * @param n new value to store + * + * @return zero if the compare failed, non-zero otherwise + */ + +static inline u_int32_t +atomic_cmpxchg32(volatile atomic_t* v, u_int32_t o, u_int32_t n) +{ + u_int32_t ret; + + __asm__ __volatile__( + " .set push \n" + " .set noat \n" + " .set mips3 \n" + "1: ll %0, %2 # __cmpxchg_u32 \n" + " bne %0, %z3, 2f \n" + " .set mips0 \n" + " move $1, %z4 \n" + " .set mips3 \n" + " sc $1, %1 \n" + " beqzl $1, 1b \n" +#ifdef CONFIG_SMP + " sync \n" +#endif + "2: \n" + " .set pop \n" + : "=&r" (ret), "=R" (*v) + : "R" (*v), "Jr" (o), "Jr" (n) + : "memory"); + + return ret; +} + +} + +// namespace oasy + +#endif /* _OASYS_ATOMIC_MIPS_H_ */